January 17, 2024
Rising interest in artificial intelligence (AI) across nearly every vertical segment of the global digital economy is expected to drive a surge in demand for hybrid bonding technology across the semiconductor industry.
According to analysts at Gartner, semiconductors designed to execute AI workloads will represent a $53.4 billion revenue opportunity for the semiconductor industry in 2023, an increase of 20.9% from 2022. AI-centric semiconductor revenue will continue to experience double-digit growth over the next few years, increasing 25.6% in 2024 to $67.1 billion and reaching $119.4 billion by 2027.
To understand the full ramifications of these market and technological forces on the industry and determine the role hybrid bonding technology will play in ensuring that chip processing power is in place to support AI use cases, we caught up with Dr. Seung Kang, who leads semiconductor strategic intellectual property (IP) and business development for Adeia.
Here is what he had to say:
Dr. Kang: It is dramatically impacting the industry because it is accelerating the need for increasingly powerful and energy-efficient computing systems, surpassing the capabilities of incumbent semiconductor platforms.
Let me elaborate.
AI workloads are computationally intensive, demanding semiconductor systems that are customized for massive parallel computing. Currently, the key drivers of such systems are a graphics processing unit (GPU) and high-bandwidth memory (HBM) which are coherently integrated with high-speed interconnects. To meet state-of-the-art AI system requirements, unprecedented performance benchmarks are needed. This is especially true when dealing with large language models. However, both processors and memory components face fundamental semiconductor scaling challenges.
GPUs and AI-customized neural processors rely on cutting-edge logic nodes that offer a smaller footprint, lower power consumption and faster speed. As the demand for computing performance continues to grow, realizing such processors on a monolithic chip — even at the most advanced node — becomes increasingly challenging. In such cases, the desired approach is to disaggregate and reassemble chips in new form factors without significant trade-offs.
Dr. Kang: Concerning memory, issues with DRAM bandwidth and capacity have existed for some time now. Since the industry first introduced HBM with four layers of vertically stacked DRAM, applications now require stacking of up to eight to twelve layers. Today, HBM applications face challenges in interconnecting more layers while simultaneously increasing throughput and improving thermal performance.
As a result, the success of next-generation AI semiconductor systems hinges on an advanced solution capable of interconnecting various dies without sacrificing the generic benefits of monolithic logic chips while also overcoming the limitations of incumbent HBMs.
There is a growing consensus in the industry that hybrid bonding technology will become widely adopted both for processors and for HBMs. Compared with other methods, hybrid bonding offers inherent advantages in high-density IO (input-output), reduced parasitic delay, shorter height and improved thermal performance.
Furthermore, it is a direct bonding process at low temperature which does not require extra materials and related process steps. In short, hybrid bonding can realize powerful multi-chip AI systems in a quasi-monolithic way.
Kang: Adeia has consistently been at the forefront of pioneering and enhancing hybrid bonding technology. In 2015, Adeia acquired intellectual property rights for hybrid bonding technology and has since maintained its commitment to organic research and development to advance this significant innovation in the semiconductor space.
Adeia not only licenses its comprehensive hybrid bonding portfolio to various semiconductor markets, including memory, logic, RF and image sensor, but also provides support to partners through technology transfers.
Hybrid bonding finds applications today in 3D heterogeneous integration scenarios where different types of chips – designed for different functions or from different suppliers – are seamlessly integrated and made interoperable.
The evolving requirements of AI systems are expected to surpass the capabilities of conventional semiconductor system architectures. This trend is driving the industry towards adopting disaggregated multi-chip configurations. Hybrid bonding is well-positioned as a compelling technology to underpin and facilitate these innovative semiconductor architectures.
Dr. Seung Kang is Vice President of Semiconductor Strategy at Adeia who currently leads strategic semiconductor programs that include technology, design, and system co-optimization. Prior to Adeia, he had a globally recognized career at Qualcomm Technologies, Inc., where he pioneered and directed the Advanced Memory Program, driving early R&D and IP validation across the semiconductor ecosystem. He also led the development of foundation logic IP for semiconductor nodes from 7 nanometers down to 3 nanometers that served Qualcomm’s flagship mobile, automotive, AI, and IoT products. Before Qualcomm, he worked at Lucent Technologies Bell Laboratories and Lawrence Berkeley National Laboratory. He obtained B.S. and M.S. degrees from Seoul National University, Korea, and a Ph.D. degree from the University of California at Berkeley. Dr. Kang is a prolific inventor with 250 U.S. patents and over 1000 patents granted globally. He has made significant contributions to the field with over 100 published papers. From 2014 to 2018, he was a Distinguished Lecturer for the IEEE Electron Device Society. He has also served as a Specially Appointed Visiting Professor at the Center for Innovative Integrated Electronic Systems, Tohoku University, Japan.
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