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Advances in Direct-to-Chip Liquid Cooling Integration

Dr. Laura Mirkarimi
Ron Zhang
Dr. Gill Fountain
Suhail Sadiq
Arianna Avellan
Reporting a new approach to silicon microchannel direct-tochip cooling and share the design performance map that is possible.
No items found.
Thermal Solutions

Design and Experimental Validation of Partitioned Flow Strategies for Optimized Microchannel Cooling

Ron Zhang
Dr. Gill Fountain
Dr. Laura Mirkarimi
Suhail Sadiq
Arianna Avellan
This work develops and experimentally validates a passive flow-partitioned silicon microchannel cold plate that maintains uniform channel geometry for manufacturability while redistributing coolant to match a strongly non-uniform XPU power map
No items found.
Thermal Solutions

3D chiplet integration with hybrid bonding
Dr. Laura Mirkarimi
Cover article in Chip Scale Review - The Future of Semiconductor Packaging
No items found.
Hybrid Bonding

Deep Convolution Neural Networks for Automatic Detection of Defects which Impact Hybrid Bonding Yield
Dr. Laura Mirkarimi
Thomas Workman
Dr. Oliver Zhao
Dominik Suwito
Bongsub Lee
An efficient and accurate optical inspection scheme where an optical microscope with automated stage and customized software collects full wafer images for designs >10 μm pad diameter.
No items found.
Hybrid Bonding

Surface Preparation Advances for Die Stacking with Hybrid Bonding
Dr. Guilian Gao
Dr. Laura Mirkarimi
Thomas Workman
Dr. Gill Fountain
Dominik Suwito
This study reports Adeia’s progress in developing a high yield, environmentally friendly process of cleaning thin die surfaces for D2W hybrid bonding.
Memory
Hybrid Bonding

High-Throughput Characterization of Nanoscale Topography for Hybrid Bonding by Optical Interferometry
Dr. Oliver Zhao
Dr. Guilian Gao
Dr. Laura Mirkarimi
Bongsub Lee
Arianna Avellan
2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
No items found.
Hybrid Bonding

Revolutionary Thermal Solutions for Hot Chips
Dr. Laura Mirkarimi
Dr. Bel Haba
Dr. Gill Fountain
Suhail Sadiq
Arianna Avellan
Focusing on DLC and alternative approaches to managing higher power densities in hot chips
Logic
Memory
Thermal Solutions

Real-time Personalized Ranking and Recommendation System for Linear TV: A Dual Dynamic Queue Approach
Dr. Ning Xu
Dr. Tao Chen
Written for presentation at the SMPTE 2022 Media and Technology Summitt & selected for publication in SMPTE Motion Imaging Journal in 2024
Video Streaming
Pay TV
Advertising Technology

Selective Enablement of L4S Transport for Latency-Sensitive Multimedia Delivery
DJ Lal
Dr. Christopher Phillips
Proposing novel methods for selectively enabling L4S, premised on judicious use of the low latency queue resource.
Gaming
Video Streaming
Networking
Spatial Computing
Wearables

Using Occluded 3D Objects for Gamified Mixed Reality Captcha
Serhad Doken
DJ Lal
This paper focused on how CAPTCHA will need to be reimagined in the new Spatial Computing world
Gaming
Spatial Computing

Automatic Visual Citation Generation for Text-to-Image Generation
Dr. Ning Xu
Serhad Doken
A novel system for generating visual citations within AI-generated images, thereby addressing copyright concerns while fostering ethical use and sharing of digital art.
No items found.
AI
Security

SoftMax-NeRF Attribute Compression with Vector-Quantized Color Tables for Point Clouds
Zhi Li
Dr. Ning Xu
A learning-based attribute codec that combines a vector-quantized color table with a compact neural radiance field
Consumer Electronics
Video Streaming
Gaming
Networking
Spatial Computing
Imaging

Adaptive Exposure Control for Mitigating Rolling Shutter Effects in CMOS Image Sensors
Dr. Ning Xu
Dr. Jean-Yves Couleaud
Toshiro Ozawa
Introducing an adaptive exposure control method that aligns the mid-exposure moments of all rows through dynamic, row-level exposure adjustment.
Consumer Electronics
Imaging

How To Address Unauthorized Broadband Sharing
Serhad Doken
DJ Lal
A technical paper prepared for presentation at SCTE TechExpo24
Video Streaming
Networking

Enhancing Linear TV Channel Surfing
Dr. Ning Xu
Dr. Tao Chen
A Real-time Personalized Ranking and Recommendation System with Dual Dynamic Queues
Pay TV
Video Streaming
Video Conferencing

Hybrid Bonding: From Concept to Commercialization
Hybrid bonding is quickly becoming recognized as the preferred permanent bonding path for forming high-density interconnects in heterogeneous integration applications, from 2DS enhanced, to 3D stacking with or without through silicon vias (TSVs), as well as MEMS and III-V applications. In this exclusive interview with Gill Fountain, Xperi, winner of the 2018 3D InCites Engineer of the Year award for his work in this area, we embark on the journey of how one hybrid bonding technology came to be.
Image Sensors
Memory
AI Hardware
Automotive
Hybrid Bonding

Recent advances and trends in Cu-Cu Hybrid Bonding IEEE
John H Lau
Memory
Hybrid Bonding

Q-band InP/CMOS receiver and transmitter beamformer channels fabricated by 3D heterogeneous integration
A. D. Carter, M. E. Urteaga, Z. M. Griffith, K. J. Lee, J. Roderick, P. Rowell, J. Bergman, S. Hong, B. Patti, C. Petteway, and G. Fountain.
Q-Band receiver and transmitter beamformer channels using 250 nm InP HBTs and 130 nm Si CMOS have been fabricated in a three-dimensional wafer-stacking platform. Room-temperature face-to-face wafer bonding is accomplished using a hybrid bonding technique (Direct Bond Interconnect®) of 2.5 micron wide, 5 micron pitch copper inlaid in silicon dioxide to form electrically active vertical interconnects.
RF Front End
Hybrid Bonding

Low-temperature hydrophobic silicon wafer bonding
Q.-Y. Tong, Q. Gan, G. Hudson, G. Fountain, Paul Enquist, Roland Scholz, U. Gösele
By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 at 300 to 400 °C compared with 700 °C conventionally achieved.
Logic
Memory
Image Sensors
Hybrid Bonding

Low temperature InP/Si wafer bonding
QY Tong, Q. Gan, G. Hudson, G. Fountain, Paul Enquist
An oxide-free, covalently bonded interface of InP/silicon wafer pairs has been realized at low temperature by plasma treatment of bonding surfaces in the reactive ion etch mode followed by a HF dip and room temperature bonding in air. The bonding energy reaches InP fracture surface energy of 630 mJ/m2 at 200 °C.
No items found.
Hybrid Bonding

Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching
QY Tong, Q. Gan, G. Fountain, G. Hudson, Paul Enquis
For bonded pairs of silicon-oxide-covered wafers, the bonding energy at low temperatures is significantly enhanced by very slight etching of the silicon oxide surfaces in diluted HF aqueous solutions prior to room temperature contacting. The bonding energy is a factor of 10 higher than standard bonded pairs to about after annealing at ⁠.
No items found.
Hybrid Bonding

Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers
Q.-Y. Tong, Q. Gan, G. Fountain, Paul Enquist, Roland Scholz, U. Gösele
The bonding energy of bonded native-oxide-covered silicon wafers treated in the or the solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over after annealing at 100 °C.
No items found.
Hybrid Bonding

Room-temperature-SiO2-SiO2-covalent-bonding
Q.-Y. Tong, G. Fountain, Paul Enquist
Room temperature covalent bonds between bonded silicon oxide layers can be realized by forming surface and subsurface absorption layers followed by terminating outmost bonding surfaces with desired bonding groups prior to bonding.
No items found.
Hybrid Bonding

Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications
Enquist, Paul & Fountain, G. & Petteway, C. & Hollingsworth, A. & Grady, H
This paper presents preliminary results of a copper-based direct bond interconnect (DBIreg) 3D integration process that has been developed to leverage foundry standard copper dual damascene and Ziptronix bond technology to achieve scalable, very low Cost-of-Ownership, 3D interconnects with minimum foundry adoption barrier.
No items found.
Hybrid Bonding

Fine Pitch Die-to-Wafer Hybrid Bonding
Laura Mirkarimi, Thomas Workman, Jeremy Theil, Gill Fountain, KM Bang, Oliver Zhao, Bongsub Lee, Cyprian Uzoh, Dominik Suwito, Gulian Gao
On behalf of the Program and Executive Committee, it is my pleasure to invite you to IEEE’s 73rd Electronic Components and Technology Conference (ECTC), which will be held at JW Marriott Orlando, Grande Lakes, Orlando, Florida from May 30 to June 2, 2023.
AI Hardware
Logic
Image Sensors
Memory
Hybrid Bonding

Die to Wafer Hybrid Bonding and Fine Pitch Considerations
T. Workman, L. Mirkarimi, J. Theil, G. Fountain, KM Bang, B. Lee, C. Uzoh, D. Suwito, G. Gao, and P. Mrozek
Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at <; 35 μm pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability.
No items found.
Hybrid Bonding

TSV module optimization for high performance silicon interposer
Andrew Cao, Thomas Dinan, Zhuowen Sun, Guilian Gao, Cyprian Uzoh, Bong-Sub Lee, Liang Wang, Hong Shen, Sitaram Arkalgud
This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation.
No items found.
Hybrid Bonding

Process compatibility of conventional and low-temperature curable organic insulation materials for 2.5D and 3D IC packaging — A user's perspective
Guilian Gao, Bong-Sub Lee, Andrew Cao, Ellis Chau
For 2.5D and 3D IC packaging, wafer back side processing often has temperature limits substantially lower than curing temperature of conventional polyimide (PI). New low temperature curable insulation materials possess very different properties and require thorough evaluation to ensure process compatibility and product reliability.
No items found.
Hybrid Bonding

Addressing Critical Assembly Challenges in 2.5D and 3D IC Assembly
Guilian Gao, Scott McGrath, Bong-Sub Lee, Cyprian Uzoh, Grant Villavicencio, Hala Shaba, Liang Frank Wang, Sitaram Arkalgud, Eric Tosaya
This event continues to grow every year as wafer-level packaging gains traction in the semiconductor industry. The overall attendance of 720 technologists from 19 countries in 2014 grew nearly 26% more attendees than the 2013 event.
AI Hardware
Logic
Image Sensors
Memory
Hybrid Bonding

Direct Bond Interconnect (DBI®) Technology as an Alternative to Thermal Compression Bonding
Guilian Gao, Gill Fountain, Paul Enquist, Cyprian Uzoh, Liang Frank Wang, Scott McGrath, Bongsub Lee, Willmar Subido, Sitaram Arkalgud, Laura Mirkarimi
Slide deck featuring DBI as an alternative to Thermal Compression Bonding
Memory
Hybrid Bonding

Direct Bond Interconnect (DBI®) For Fine-Pitch Bonding in 3D and 2.5D Integrated Circuits
Gill Fountain, Bongsub Lee, Guilian Gao, Cyprian Uzoh, Scott McGrath, Paul Enquist, Sitaram Arkalgud and Laura Mirkarimi
Leading-edge technology integration, high-bandwidth and low-power data access call for vertical stacking of semiconductor devices with very fine pitch interconnects. To address this demand, a unique technology referred to as Direct Bond Interconnect (DBI®) which was invented by Ziptronix [1] is being further developed for die to wafer applications.
No items found.
Hybrid Bonding
Thermal Solutions

Accessible Determination of Die-to-Wafer Bond Strength with the Schwickerath Test
Shuai Shao, Yuling Niu, Jing Wang, Seungbae Park, and Bongsub Lee
Die-to-wafer or wafer-to-wafer direct bonding has been drawing significant attention and undergoing rapid development for its various applications in three-dimensional integrated circuits (3D-IC), such as image sensors, micro-electro-mechanical system (MEMS) sensors, and stacked memory products.
Memory
Hybrid Bonding

Low Warpage and Improved 2.5/3DIC Process Capability with a Low Stress Polyimide Dielectric
Robert L. Hubbard and Bong-Sub Lee
One of the key enablers for the successful integration of 3-D interconnects using the Through-Silicon Via (TSV) schemes is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate.
Memory
Imaging

Manufacturing Readiness of BVA™ Technology for Ultra-High Bandwidth Package-on-Package
Rajesh Katkar; Ashok Prabhu; Rey Co; Wael Zohni
Bond Via Array (BVA) technology has been developed to enable more than 1000 vertical connections between memory and processor components in a standard outline Package-on-Package (PoP) configuration. This higher density interconnect more than doubles current PoP capability and thereby addresses next generation wide IO mobile device demands for increased bandwidth [1]-[3].
No items found.
Hybrid Bonding

Package-on-Package with Very Fine Pitch Interconnects for High Bandwidth
Ilyas Mohammed, Reynaldo Co and Rajesh Katkar
Computing platforms are trending towards multi-core and low power processors coupled with high bandwidth memory in close proximity for both client and cloud applications. The most critical feature to keep increasing the performance is the processor-memory interconnect.
Memory
Hybrid Bonding

Ultra-Fine Pitch Package on Package Solution for High Bandwidth Mobile Applications
Rajesh Katkar, Zhijun Zhao, Ron Zhang, Rey Co and Laura Mirkarimi
Multi-Core Processors: Significantly increased the need for multiple memory channels, channel bandwidth and total memory
Logic
Memory
Hybrid Bonding

3D Packaging for High Computing with Wide IO Processor-Memory Interface
Ilyas Mohammed, Ron Zhang and Rajesh Katkar
Bond-Via-Array (BVA™) technology has been developed to address the high density interconnect requirements of the next generation of package-on-package (PoP) solutions.
Memory
Hybrid Bonding

Applications of 3D X-Ray Microscopy for Advanced Package Development
K. Fahey and R. Estrada, L. Mirkarimi, R. Katkar, D. Buckminster and M. Huynh
This paper describes the utilization of non-destructive imaging using 3D x-ray microscopy for package development and failure analysis. Four case studies are discussed to explain our methodology and its impact on our advanced packaging development effort.
Logic
Memory
No items found.

Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages
Rajesh Katkar, Michael Huynh, Ron Zhang and Laura Mirkarimi
Improved electrical and thermal performance due to shorter electrical paths between the die and the substrate. Better power ground distribution. High packaging density and scalability
Logic
Memory
RF Front End
AI Hardware
Hybrid Bonding

Electromigration Performance of Pb-Free µPILR™ Flip-Chip Packages
Rajesh Katkar and Laura Mirkarimi
The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages.
Logic
Memory
Hybrid Bonding

Analytical and Experimental Studies of 2.5D Silicon Interposer Warpage: Impact of Assembly Sequences, Material Selection and Process Parameters
Mirkarimi, L., Zhang, R.
We compare the influence of different assembly sequences, process parameters and material properties on the resulting package and interposer warpage in 3D stacking configurations.
AI Hardware
Memory
Thermal Solutions

Mechanical Strength Characterization of Direct Bond Interfaces for 3D-IC and MEMS Applications
Bongsub Lee
Direct bond interconnect is gaining traction in a variety of applications including imaging and MEMS sensors as well as fine-pitch 3D-IC memory stacks, due to the room temperature bond with enhanced bond strength. The all-inorganic interface offers advantages of superior thermal performance as well.
Memory
Hybrid Bonding

Thermal and Electrical Performance of Direct Bond Interconnect Technology for 2.5 and 3D Integrated Circuits
A. Agrawal
Currently thermo-compression bonding (TCB) of solder capped micro bumps is the industry standard for high bandwidth memory (HBM) packaging. However, the assembly complexity and high cost has limited its high volume adoption.
Memory
Hybrid Bonding

Development of Low Temperature Direct Bond Interconnect Technology for Die-To-Wafer and Die-To-Die Applications-Stacking, Yield Improvement, Reliability Assessment
G. Gao, L. Mirkarimi, T. Workman, G. Guevara, J. Theil, C. Uzoh, G. Fountain, B. Lee, P. Mrozek, M. Huynh, R. Katkar
The Direct Bond Interconnect technology (DBI), commonly referred to as low temperature hybrid bonding, is an attractive bonding technology with the potential of much finer pitch and higher throughput than any solder based microbump bonding.
Memory
Hybrid Bonding

Low-Temperature Cu Interconnect with Chip-to-Wafer Hybrid Bonding
G. Gao, L. Mirkarimi, C. Rudolph, T. Werner, A. Hanisch, T. Workman, G. Fountain, J. Theil, G. Guevara, P. Liu, and B. Lee
Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection.
Memory
Hybrid Bonding

Nanoscale Topography Characterization for Direct Bond Interconnect
B. Lee, P. Mrozek, G. Fountain, J. Posthill, J. Theil, G. Gao, R. Katkar, and L. Mirkarimi
Hybrid bonding achieves mechanical and electrical connection between device wafers or dies, by directly joining dielectric and metal surfaces to form an all-inorganic interface. This direct bond interconnect (DBI) technology enables very fine pitch interconnects for high bandwidth interfaces.
AI Hardware
Logic
Memory
Image Sensors
Hybrid Bonding

Chip to Wafer Hybrid Bonding with Cu Interconnect: Manufacturability and High Volume Compatibility Study
G. Gao, T. Workman, L. Mirkarimi, G. Fountain, J. Theil, G. Guervara, B. Lee, P. Liu, and P. Mzorek
Solder reflow technology is volume manufacturing ready to an interconnect pitch of about 60um for two main reasons. Solder has the ability to compensate for height differences among the interconnects on a die or package through the melting and re-solidification process.
Logic
Memory
Hybrid Bonding

Recent Developments in Fine Pitch Wafer-to-Wafer Hybrid Bonding with Copper Interconnect
J. A. Theil, L. Mirkarimi, G. Fountain, G. Gao, and R. Katkar
3D architectures are increasingly making their way into commercial products such as image sensors and 3D memory. While hybrid bonding exists today in wafer-to-wafer (W2W) format in high volume manufacturing, the proliferation of this technology continues to accelerate.
Logic
Memory
Hybrid Bonding

Die to Wafer Stacking with Low Temperature Hybrid Bonding
G. Gao, L. Mirkarimi, G. Fountain, T. Workman, J. Theil, G. Guevara, C. Uzoh, D. Suwito, B. Lee, K. M. Bang, R. Katkar
The direct bond interconnect (DBI®) Ultra technology, a low-temperature die-to-wafer (D2W) and die-to-die (D2D) hybrid bond, is a platform technology to reliably achieve submicron interconnect pitches. A reliable D2W and D2D assembly with submicron pitch capability will enable widespread disaggregation and chiplet architecture innovation.
Memory
Hybrid Bonding

Low Temperature Hybrid Bonding for Die to Wafer Stacking Applications
G. Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, T. Workman, C. Uzoh, G. Guevara, B. Lee, M. Huynh, and P. Mrozek
The direct bond interconnect (DBI®) technology is a platform technology that offers a hermetically sealed hybrid bond with solid metal-metal (Cu-Cu is the most common) interconnect at a relatively low thermal budget. The Xperi wafer to wafer hybrid bonding technology has been in high volume production since 2015.
Memory
Hybrid Bonding

Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications
G. Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, T. Workman, C. Uzoh, B. Lee, KM Bang, G. Guevara
The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015.
Memory
Hybrid Bonding

The Influence of Microstructure on Thermal Budget in Hybrid Bonding
L. Mirkarimi, C. Uzoh, D. Suwito, G. Fountain, T. Workman, B. Lee, J. Theil, G. Gao,
Advanced package modules built with a hybrid bonding technology offer enhanced thermal performance, reliability, and scalability with the Cu-Cu interconnect. Direct Bond Interconnect (DBI®) Ultra technology is a die-to-wafer (D2W) or die-to-die (D2D) high volume manufacturing compatible process that offers handling die on tape, assembly at room temperature, and low temperature interconnect formation.
Memory
Hybrid Bonding

Analysis of Die Edge Bond Pads in Hybrid Bonded Multi-Die Stacks
J. A. Theil, T. Workman, D. Suwito, L. Mirkarimi, G. Fountain, KM Bang, G. Gao, B. Lee, P. Mrozek, C. Uzoh, M. Huynh, and O. Zhao
Direct Bond Interconnect (DBI®) is a hybrid bonding technique that is currently being adopted in the semiconductor industry due to its versatility at enabling zero standoff bonding. It is used in a large segment of products such as Back Side Illuminated (BSI) CMOS image sensors and starting to appear in other applications including 3DNAND.
Memory
Hybrid Bonding

HVM CMP Process Development for Advanced Direct Bond Interconnect (DBI)
C. Rudolph, H. Wachsmuth, P. Gansauer, T. Werner, M. Junhaehnel, G. Fountain, J. Theil, L. Mirkarimi,
Direct bonding is a spontaneous dielectric-to-dielectric bond at room temperature with a metal-to-metal connection (here Cu-to-Cu bond) by a low temperature batch annealing process (200°C – 300°C). Therefore, the direct bonding process is attractive for heterogeneous integration and has several advantages over the micro bump bonding with solder [1, 2]. Furthermore, the interconnect density and scaling of interconnects is less limited for this metal cap free bonding process.
No items found.
Hybrid Bonding

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