DBI wafer-to-wafer hybrid bonding is ideal for smaller, high yielding die-like image sensors, antenna switches and, more recently, 3D NAND. In contrast, DBI Ultra die-to-wafer hybrid bonding is suitable for larger die, such as DRAM, microprocessors, graphics processors and SoCs. DBI Ultra allows known good die to be bonded to other known good die, allowing for high yielding, multi-die stacked 2.5D and 3D assemblies.
- USAGE: Die-to-wafer and die-to-die bonding with electrical interconnect
- HOW: Wafer surfaces are planarized and bond pads are recessed in a dielectric layer; wafers are diced, cleaned, and activated; known good die are picked, aligned and bonded at room temperature on top of other known good die; metal interconnect is formed during low-temperature batch anneal
- SOLUTIONS: High Bandwidth Memory (HBM) stacks of 4, 8, 12, 16 or more die, 2.5D / 3D integration of memory with CPUs, GPUs, FPGAs and/or SoCs for high performance computing
- MARKETS: Data centers, autonomous vehicles, gaming, 5G infrastructure, data storage & supercomputers
Ultra fine pitch interconnect enables high bandwidth
Chemical bond without external bond pressure
Low temperature process
Better thermal performance
Zero standoff & thin profile
Low cost with high bonding throughput
DBI Ultra makes it possible to manufacture 4, 8, 12 or 16-high 3D stacked memory while meeting the stringent packaging height and performance requirements for next generation high-performance computing. DBI Ultra enables high bandwidth and high performance 2.5D and 3D integration of memory, CPU, GPU, FPGA or SoC.
DBI® Ultra Die-to-Wafer Hybrid Bonding
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