DBI can also minimize the need for Thru Silicon Vias (TSVs) by allowing interconnection to occur at the bonding surface, improving electrical performance. Incorporating dielectric bonding eliminates the need for underfill while providing excellent thermal performance, reliability and hermeticity, if required.
- USAGE: Wafer-to-wafer bonding with electrical interconnect
- HOW: Wafer surface is planarized and bond pads are recessed in a dielectric layer; wafers are aligned and bonded at room temperature; metal interconnect is formed during low-temperature batch anneal
- SOLUTIONS: BSI Image Sensor, DRAM, MEMS, RF
- MARKETS: Consumer electronics (smartphones, tablets, laptops, digital cameras, televisions, gaming consoles) IoT, industrial, automotive and medical
Very fine pitch interconnect
Chemical bond without external bond pressure
Low temperature process
Minimal warpage or delamination problems
Bond between wafers with same or different thermal expansion rate
During processing, industry-standard dielectrics surfaces such as silicon oxide and silicon carbide nitride, with embedded metal bond pads that are typically of copper or nickel, are polished to achieve minimal surface roughness. Simultaneously, the metal bond pads are slightly dished. Polishing and dishing are readily achieved using standard chemical mechanical polishing (CMP) tools. Nitrogen-based chemistries are applied through conventional plasma etch tools. Prepared wafers can then be simply aligned and placed together, resulting in the spontaneous formation of strong chemical bonds between the prepared surfaces. After a moderate batch anneal, the DBI bond pads expand together to form a homogeneous metallic interconnect with grain growth across the bond interface. The chemical bond between oxides is significantly strengthened, ensuring high reliability without requiring underfill.
High Density Low Cost Stacked 3D NAND with Hybrid Bonding
Pixel-Level 3D Integration for Advanced Stacked CMOS Image Sensors
3D Integration for MEMS Devices
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