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Accessible Determination of Die-to-Wafer Bond Strength with the Schwickerath Test


Engineering Fracture Mechanics

April 21, 2020

Shuai Shao, Yuling Niu, Jing Wang, Seungbae Park, and Bongsub Lee

Die-to-wafer or wafer-to-wafer direct bonding has been drawing significant attention and undergoing rapid development for its various applications in three-dimensional integrated circuits (3D-IC), such as image sensors, micro-electro-mechanical system (MEMS) sensors, and stacked memory products.

Chip to Wafer Hybrid Bonding with Cu Interconnect: Manufacturability and High Volume Compatibility Study



October 20, 2019

G. Gao, T. Workman, L. Mirkarimi, G. Fountain, J. Theil, G. Guervara, B. Lee, P. Liu, and P. Mzorek

Solder reflow technology is volume manufacturing ready to an interconnect pitch of about 60um for two main reasons. Solder has the ability to compensate for height differences among the interconnects on a die or package through the melting and re-solidification process.

Recent Developments in Fine Pitch Wafer-to-Wafer Hybrid Bonding with Copper Interconnect



October 4, 2019

J. A. Theil, L. Mirkarimi, G. Fountain, G. Gao, and R. Katkar

3D architectures are increasingly making their way into commercial products such as image sensors and 3D memory. While hybrid bonding exists today in wafer-to-wafer (W2W) format in high volume manufacturing, the proliferation of this technology continues to accelerate.

Low-Temperature Cu Interconnect with Chip-to-Wafer Hybrid Bonding



May 12, 2019

G. Gao, L. Mirkarimi, C. Rudolph, T. Werner, A. Hanisch, T. Workman, G. Fountain, J. Theil, G. Guevara, P. Liu, and B. Lee

Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection.

Nanoscale Topography Characterization for Direct Bond Interconnect



May 2, 2019

B. Lee, P. Mrozek, G. Fountain, J. Posthill, J. Theil, G. Gao, R. Katkar, and L. Mirkarimi

Hybrid bonding achieves mechanical and electrical connection between device wafers or dies, by directly joining dielectric and metal surfaces to form an all-inorganic interface. This direct bond interconnect (DBI) technology enables very fine pitch interconnects for high bandwidth interfaces.

Development of Low Temperature Direct Bond Interconnect Technology for Die-To-Wafer and Die-To-Die Applications-Stacking, Yield Improvement, Reliability Assessment



October 23, 2018

G. Gao, L. Mirkarimi, T. Workman, G. Guevara, J. Theil, C. Uzoh, G. Fountain, B. Lee, P. Mrozek, M. Huynh, R. Katkar

The Direct Bond Interconnect technology (DBI), commonly referred to as low temperature hybrid bonding, is an attractive bonding technology with the potential of much finer pitch and higher throughput than any solder based microbump bonding.

Direct bond interconnect is gaining traction in a variety of applications including imaging and MEMS sensors as well as fine-pitch 3D-IC memory stacks, due to the room temperature bond with enhanced bond strength. The all-inorganic interface offers advantages of superior thermal performance as well.

Hybrid Bonding: From Concept to Commercialization


Blog and 3D InCites Magazine Article

April 2, 2018

Hybrid bonding is quickly becoming recognized as the preferred permanent bonding path for forming high-density interconnects in heterogeneous integration applications, from 2DS enhanced, to 3D stacking with or without through silicon vias (TSVs), as well as MEMS and III-V applications. In this exclusive interview with Gill Fountain, Xperi, winner of the 2018 3D InCites Engineer of the Year award for his work in this area, we embark on the journey of how one hybrid bonding technology came to be.

Q-band InP/CMOS receiver and transmitter beamformer channels fabricated by 3D heterogeneous integration


Proceedings 2017 IEEE International Microwave Symposium

June 16, 2017

A. D. Carter, M. E. Urteaga, Z. M. Griffith, K. J. Lee, J. Roderick, P. Rowell, J. Bergman, S. Hong, B. Patti, C. Petteway, and G. Fountain.

Q-Band receiver and transmitter beamformer channels using 250 nm InP HBTs and 130 nm Si CMOS have been fabricated in a three-dimensional wafer-stacking platform. Room-temperature face-to-face wafer bonding is accomplished using a hybrid bonding technique (Direct Bond Interconnect®) of 2.5 micron wide, 5 micron pitch copper inlaid in silicon dioxide to form electrically active vertical interconnects.

Currently thermo-compression bonding (TCB) of solder capped micro bumps is the industry standard for high bandwidth memory (HBM) packaging. However, the assembly complexity and high cost has limited its high volume adoption.

Direct Bond Interconnect (DBI®) For Fine-Pitch Bonding in 3D and 2.5D Integrated Circuits


Pan Pacific Microelectronics Symposium

February 5, 2017

Gill Fountain, Bongsub Lee, Guilian Gao, Cyprian Uzoh, Scott McGrath, Paul Enquist, Sitaram Arkalgud and Laura Mirkarimi

Leading-edge technology integration, high-bandwidth and low-power data access call for vertical stacking of semiconductor devices with very fine pitch interconnects. To address this demand, a unique technology referred to as Direct Bond Interconnect (DBI®) which was invented by Ziptronix [1] is being further developed for die to wafer applications.

Direct Bond Interconnect (DBI®) Technology as an Alternative to Thermal Compression Bonding



October 12, 2016

Guilian Gao, Gill Fountain, Paul Enquist, Cyprian Uzoh, Liang Frank Wang, Scott McGrath, Bongsub Lee, Willmar Subido, Sitaram Arkalgud, Laura Mirkarimi

Slide deck featuring DBI as an alternative to Thermal Compression Bonding

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