Semi Research

This paper presents preliminary results of a copper-based direct bond interconnect (DBIreg) 3D integration process that has been developed to leverage foundry standard copper dual damascene and Ziptronix bond technology to achieve scalable, very low Cost-of-Ownership, 3D interconnects with minimum foundry adoption barrier.

Room temperature covalent bonds between bonded silicon oxide layers can be realized by forming surface and subsurface absorption layers followed by terminating outmost bonding surfaces with desired bonding groups prior to bonding.

For bonded pairs of silicon-oxide-covered wafers, the bonding energy at low temperatures is significantly enhanced by very slight etching of the silicon oxide surfaces in diluted HF aqueous solutions prior to room temperature contacting. The bonding energy is a factor of 10 higher than standard bonded pairs to about after annealing at ⁠.

The bonding energy of bonded native-oxide-covered silicon wafers treated in the or the solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over after annealing at 100 °C.

An oxide-free, covalently bonded interface of InP/silicon wafer pairs has been realized at low temperature by plasma treatment of bonding surfaces in the reactive ion etch mode followed by a HF dip and room temperature bonding in air. The bonding energy reaches InP fracture surface energy of 630 mJ/m2 at 200 °C.

By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 at 300 to 400 °C compared with 700 °C conventionally achieved.