Papers & Publications

Recent advances and trends in Cu-Cu hybrid bonding are investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of Cu-Cu bump-less hybrid bonding.

We compare the influence of different assembly sequences, process parameters and material properties on the resulting package and interposer warpage in 3D stacking configurations.

This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation.

For 2.5D and 3D IC packaging, wafer back side processing often has temperature limits substantially lower than curing temperature of conventional polyimide (PI). New low temperature curable insulation materials possess very different properties and require thorough evaluation to ensure process compatibility and product reliability.

The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding platform, offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. The value of DBI® Ultra can be realized in diverse products ranging from very small die to reticle-size large die in applications such as RF, sensors, microcontrollers, GPUs, and FPGAs.

In this paper we examine the influence of microstructural engineering of the Cu pad on the thermal budget required to obtain strong metallurgical Cu-Cu bonds, producing reductions in final anneal temperature.

Hybrid bond pad performance was studied based on proximity to the die edge for both single and multi-die configurations to establish design guidelines and understand the processing and layout effects.

Learn about chemical mechanical polishing (CMP), a crucial preparation step for successful wafer-to-wafer hybrid bonding, enabling rapid adoption of hybrid bonding in high-volume manufacturing (HVM).

The DBI® Ultra hybrid bonding technology is now ready for industry adoption and ramp to manufacturing. The value of the hybrid bonded Cu-Cu technology may be realized at various interconnect pitches for different applications. In this paper, we report on 5-die stack hybrid bonded module with TSV and the latest fabrication, assembly process, electrical testing, and reliability performance.

Thermo-compression bonding (TCB) of solder capped micro bumps is the industry standard for high bandwidth memory (HBM) packaging. However, the assembly complexity and high cost has limited its high-volume adoption. Direct Bond Interconnect technology is an attractive alternate solution due to the instantaneous bond at room temperature. Two dielectric surfaces are bonded at room temperature, while the metal interconnection (Cu to Cu in most applications) is completed during a subsequent low temperature anneal (1500C – 3000C). The initial dielectric bonding process is performed at ambient temperature and pressure with no adhesive or other filler materials. Bonding takes place instantaneously once the two surfaces are brought into contact. Batch anneal is carried out in a conventional oven. Compared to thermal compression bonding, it has advantages of higher throughput and yield which drive the overall bonding costs down.