Papers & Publications

Slide deck featuring DBI as an alternative to Thermal Compression Bonding

The focus of this technical presentation is on improving electrical and thermal performance of flip chip technology by creating shorter electrical paths between the die and the substrate. Reliability testing of Cu pillar on die interconnects and Cu pillar on substrate interconnects is detailed including experimental results, failure analysis and discussion.

Bond-Via Array (BVA™) technology has been developed to address the high-density interconnect requirements of the next generation of package-on-package (PoP) solutions. This technology, while utilizing conventional assembly processes and equipment can provide more than 1000 interconnections between the memory and the logic packages when stacked in a PoP format within a standard PoP package footprint.

This presentation outlines trends in mobile computing, existing PoP solutions, Bond Via Array (BVA) for wide IO and PoP, and BVA PoP scalability. Reliability testing of PoP prototypes is described, including test vehicle design and assembly, and test conditions. Test results identified a non-TSV PoP solution offering both high reliability and ultra-high bandwidth between logic and memory devices. Notably, this PoP package enabled greater than 1000 logic to memory interconnects within a standard 14mm x 14mm footprint and with interconnect pitch from 0.4mm to less than 02mm in 1 to 6 rows on 2 or all 4 sides.

One key enabler for the successful integration of 3-D interconnects using the Through-Silicon Via (TSV) schemes is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate. The synchrotron-sourced X-ray microdiffraction technique has been recognized to allow important advantages compared to other techniques in characterization of the mechanical stresses in a TSV sample. This approach has been used to study Cu TSV samples from SK Hynix, Inc. earlier as well as more recently from SEMATECH, and we have found interesting differences in the stress states of the Cu TSV. We proposed a possible explanation of the observed differences. This fundamental understanding could lead to improved stress control and hence reliability in the Cu TSV samples, as well as to reduce its impact to the silicon electron mobility and hence to device performance in general.

This paper presents bonding and electrical yield results with a test vehicle design that demonstrates high-density, fine pitch bonding with high-yield. The test vehicle consists of daisy chain test patterns with 4 μm bonding pitch with 115k links and covers a bond area of 3.61 mm ² . The process flow enables high throughput processing with room temperature bonding and post-bond batch anneal. The process shows minimum electrical yield greater than 98% across all wafers. Longer chains of 500k links with a 3 μm diameter pad with a 10 μm pitch show similar yields. Temperature cycling and autoclave tests of the 3 μm diameter pad test structures showed a robust Cu-Cu interconnection and superior reliability performance.

This paper presents preliminary results of a copper-based direct bond interconnect (DBIreg) 3D integration process that has been developed to leverage foundry standard copper dual damascene and Ziptronix bond technology to achieve scalable, very low Cost-of-Ownership, 3D interconnects with minimum foundry adoption barrier. 

This paper describes the utilization of non-destructive imaging using 3D x-ray microscopy for package development and failure analysis. Four case studies are discussed to explain our methodology and its impact on our advanced packaging development effort.

Room temperature covalent bonds between bonded silicon oxide layers can be realized by forming surface and subsurface absorption layers followed by terminating outmost bonding surfaces with desired bonding groups prior to bonding.

Solder reflow technology is volume manufacturing ready. Unfortunately, it appears to be limited to a minimum pitch of 40 µm. Therefore, the industry is searching for a solid-state bonding technology to enable further pitch scaling. The candidate technology should have the following key attributes: 1) a mechanism to precisely control the metal height variation to prevent open joints, 2) high-assembly throughput, 3) low-temperature for certain applications, and 4) a pathway to future generations of chip scaling. Direct Bond Interconnect (DBI®) technology achieves all attributes listed above.