Current DRAM advanced chip stack packages, such as the high bandwidth memory (HBM), use through silicon via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection. The bonding process has low throughput and cannot overcome the challenge of scaling below 40 μm pitch. The pursuit of fine pitch die stacking with TSV interconnect using hybrid bonding is pervasive in the packaging industry today due to the promise of improved performance. This paper presents the latest development in chip-to-wafer hybrid bonding and demonstrates the low-temperature annealing capability and integration with TSV.

Hybrid bonding achieves mechanical and electrical connection between device wafers or dies, by directly joining dielectric and metal surfaces to form an all-inorganic interface. This Direct Bond Interconnect (DBI®) technology enables very fine pitch interconnects for high-bandwidth interfaces. DBI® is currently used for mass production of image sensors and is actively investigated for NAND, DRAM, and MEMS applications. Characterizing and controlling nanoscale topography are essential for this type of bonding. After chemical mechanical polishing (CMP), the dielectric surface (usually SiO ₂ ) should have high-planarity and sub-nm roughness, and the metal surface (usually Cu) should be slightly recessed below the dielectric surface in general. Atomic force microscopy (AFM) is a critical technique required to monitor the CMP process module and ensure a robust manufacturing process. While AFM and related techniques have been known for decades, nanoscale or sub-nm scale characterization for DBI® requires careful choice of the analysis configurations and parameters to avoid misinterpretation. Here we discuss key considerations for AFM analysis, extraordinary AFM artifacts in the relative heights of the Cu and SiO ₂ areas, and topographic characteristics of Cu/SiO ₂ surface for successful hybrid bonding. 

The direct bond interconnect technology, commonly referred to as low-temperature hybrid bonding, is an attractive bonding technology with the potential of much finer pitch and higher throughput than solder-based micro-bump bonding. The unique challenges include producing shallow, uniform and well-controlled Cu recess on Cu bond pads of 5 um or greater, which is substantially larger than what is normally used in wafer-to-wafer bonding and particle minimization on die surface prior to bonding. In this paper, we present the latest development of our chemical mechanical polish (CMP) technology to produce uniform shallow Cu recess on 15um circular bond pads. 

Direct bond interconnect is gaining traction in a variety of applications including imaging and MEMS sensors as well as fine-pitch 3D-IC memory stacks, due to the room temperature bond with enhanced bond strength. The all-inorganic interface offers advantages of superior thermal performance as well. To analyze the quality of wafer-to-wafer bonding, the double cantilever beam (DCB) technique using razor-blade insertion is a widely practiced technique. In contrast, the techniques to evaluate the direct bond quality of die-to-wafer samples or MEMS cavity samples are not widely established. In this study, we developed procedures to analyze the mechanical quality of direct bond in die-to-wafer samples and MEMS cavity samples. 

Hybrid bonding is quickly becoming recognized as the preferred permanent bonding path for forming high-density interconnects in heterogeneous integration applications, from 2DS enhanced, to 3D stacking with or without through silicon vias (TSVs), as well as MEMS and III-V applications. In this exclusive interview with Gill Fountain, Xperi, winner of the 2018 3D InCites Engineer of the Year award for his work in this area, we embark on the journey of how one hybrid bonding technology came to be.

Q-Band receiver and transmitter beamformer channels using 250 nm InP HBTs and 130 nm Si CMOS have been fabricated in a three-dimensional wafer-stacking platform. Room-temperature face-to-face wafer bonding is accomplished using a hybrid bonding technique (Direct Bond Interconnect®) of 2.5 micron wide, 5-micron pitch copper inlaid in silicon dioxide to form electrically active vertical interconnects. 3-bit amplitude and 4-bit phase modulation receive and transmit channels are characterized. At 40 GHz, the receiver and transmitter chains have more than 25 dB gain, with 6 dB variable gain tuning, and less than 5° RMS phase error. The transmitter saturated output power is 20.3 dBm. To the authors' knowledge, this is the first demonstration of wafer-scale three-dimensional integration of Si and InP MMICs towards RF beamforming applications.