Papers & Publications

For bonded pairs of silicon-oxide-covered wafers, the bonding energy at low temperatures is significantly enhanced by very slight etching of the silicon oxide surfaces in diluted HF aqueous solutions prior to room temperature contacting. The bonding energy is a factor of 10 higher than standard bonded pairs to about 2000 mJ/m2 after annealing at 100oC.

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages.

The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO₃ ∕ H₂O ∕ HF or the HNO₃ ∕ HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ ∕ m² after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

An oxide-free, covalently bonded interface of InP/silicon wafer pairs has been realized at low temperature by plasma treatment of bonding surfaces in the reactive ion etch mode followed by a HF dip and room temperature bonding in air. The bonding energy reaches InP fracture surface energy of 630 mJ/m² at 200 °C.

Wafer-to-wafer (W2W) direct bond interconnect technology has been in high-volume manufacturing for several years. We have been reporting development for extending this technology from wafer-to-wafer (W2W) to die-to-wafer (D2W) and die-to-die (D2D) applications over the past few years. In this paper, we assess the high-volume readiness of the technology using a die-to-wafer and die-to-die stacking. Critical enabling factors include the CMP process for bonding surface planarization and Cu recess control, metrology tools for CMP process control and verification, and compatibility with the silicon supply chain for assembly. Other important factors include the singulation technology and die handling.

By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 at 300 to 400 °C compared with 700 °C conventionally achieved.

Computing platforms are trending towards multi-core and low power processors coupled with high bandwidth memory in close proximity for both client and cloud applications. The most critical feature to keep increasing the performance is the processor-memory interconnect. This is best achieved by placing memory on top of the processor and connecting them through very short and high number of interconnects. However, current 3D packages are limited in number of interconnects primarily due to their low aspect ratio. A new PoP interconnect technology is presented that offers very fine pitch (0.2mm and lower) and high aspect ratio (10:1 and higher), hence enabling high bandwidth between the processor and memory. 

Die-to-wafer or wafer-to-wafer direct bonding has been drawing significant attention and undergoing rapid development for its various applications in three-dimensional integrated circuits (3D-IC), such as image sensors, micro-electro-mechanical system (MEMS) sensors, and stacked memory products. The bond strength is one of the most considerable factors that affect the reliability of such stacked devices. Measurement of wafer-to-wafer bond strength is normally performed by the razor blade method, but there was no such well-established technique for die-to-wafer direct bond. To characterize the die-to-wafer bond strength accurately and conveniently, this work introduced the Schwickerath three-point bending test and derived an analytical solution of bond energy, which does not require initial crack preparation. To examine the correctness of applying this method in a novel area, finite element method (FEM) and razor blade experiments on equivalent samples were conducted. Furthermore, the annealing effect on die-to-wafer bond strength was studied. Top die thickness, loading rate in three-point bending test, and the compensation factor of analytical solution are discussed and summarized in this study.