We compare the influence of different assembly sequences, process parameters and material properties on the resulting package and interposer warpage in 3D stacking configurations.

Computing platforms are trending towards multi-core and low power processors coupled with high bandwidth memory in close proximity for both client and cloud applications. The most critical feature to keep increasing the performance is the processor-memory interconnect. This is best achieved by placing memory on top of the processor and connecting them through very short and high number of interconnects. However, current 3D packages are limited in number of interconnects primarily due to their low aspect ratio. A new PoP interconnect technology is presented that offers very fine pitch (0.2mm and lower) and high aspect ratio (10:1 and higher), hence enabling high bandwidth between the processor and memory. 

This presentation outlines trends in mobile computing, existing PoP solutions, Bond Via Array (BVA) for wide IO and PoP, and BVA PoP scalability. Reliability testing of PoP prototypes is described, including test vehicle design and assembly, and test conditions. Test results identified a non-TSV PoP solution offering both high reliability and ultra-high bandwidth between logic and memory devices. Notably, this PoP package enabled greater than 1000 logic to memory interconnects within a standard 14mm x 14mm footprint and with interconnect pitch from 0.4mm to less than 02mm in 1 to 6 rows on 2 or all 4 sides.

One key enabler for the successful integration of 3-D interconnects using the Through-Silicon Via (TSV) schemes is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate. The synchrotron-sourced X-ray microdiffraction technique has been recognized to allow important advantages compared to other techniques in characterization of the mechanical stresses in a TSV sample. This approach has been used to study Cu TSV samples from SK Hynix, Inc. earlier as well as more recently from SEMATECH, and we have found interesting differences in the stress states of the Cu TSV. We proposed a possible explanation of the observed differences. This fundamental understanding could lead to improved stress control and hence reliability in the Cu TSV samples, as well as to reduce its impact to the silicon electron mobility and hence to device performance in general.

Bond-Via Array (BVA™) technology has been developed to address the high-density interconnect requirements of the next generation of package-on-package (PoP) solutions. This technology, while utilizing conventional assembly processes and equipment can provide more than 1000 interconnections between the memory and the logic packages when stacked in a PoP format within a standard PoP package footprint.

The focus of this technical presentation is on improving electrical and thermal performance of flip chip technology by creating shorter electrical paths between the die and the substrate. Reliability testing of Cu pillar on die interconnects and Cu pillar on substrate interconnects is detailed including experimental results, failure analysis and discussion.